A memory controller, also known as memory chip controller (MCC) or a memory controller unit (MCU), is a digital circuit that manages the circulate of information going to and from a computer's foremost memory. When a memory controller is integrated into one other chip, Memory Wave resembling an integral a part of a microprocessor, it is often called an built-in memory controller (IMC). Memory controllers comprise the logic necessary to read and write to dynamic random-access memory (DRAM), and to offer the critical memory refresh and other functions. Studying and writing to DRAM is carried out by deciding on the row and column knowledge addresses of the DRAM as the inputs to the multiplexer circuit, the place the demultiplexer on the DRAM uses the converted inputs to select the correct memory location and return the info, which is then handed back by means of a multiplexer to consolidate the info in order to scale back the required bus width for the operation. Memory controllers' bus widths vary from 8-bit in earlier systems, to 512-bit in more difficult methods, the place they are typically carried out as 4 64-bit simultaneous memory controllers operating in parallel, although some function with two 64-bit memory controllers being used to access a 128-bit memory machine.

Some memory controllers, such as the one integrated into PowerQUICC II processors, embrace error detection and correction hardware. Many modern processors are additionally integrated memory management unit (MMU), which in many working systems implements virtual addressing. On early x86-32 processors, the MMU is integrated within the CPU, however the memory controller is normally a part of northbridge. Older Intel and PowerPC-based computer systems have memory controller chips which might be separate from the main processor. Typically these are built-in into the northbridge of the computer, also generally referred to as a memory controller hub. Most modern desktop or workstation microprocessors use an built-in memory controller (IMC), MemoryWave Official including microprocessors from Intel, AMD, and people constructed across the ARM architecture. Previous to K8 (circa 2003), AMD microprocessors had a memory controller applied on their motherboard's northbridge. In K8 and later, AMD employed an built-in memory controller. Likewise, until Nehalem (circa 2008), Intel microprocessors used memory controllers applied on the motherboard's northbridge.

Nehalem and later switched to an built-in memory controller. Other examples of microprocessor architectures that use integrated memory controllers include NVIDIA's Fermi, IBM's POWER5, and Sun Microsystems's UltraSPARC T1. While an built-in memory controller has the potential to extend the system's performance, similar to by decreasing memory latency, it locks the microprocessor to a specific type (or types) of memory, forcing a redesign in an effort to help newer memory technologies. When DDR2 SDRAM was introduced, AMD launched new Athlon 64 CPUs. These new fashions, with a DDR2 controller, use a unique bodily socket (generally known as Socket AM2), in order that they are going to solely slot in motherboards designed for the brand new type of RAM. When the memory controller is just not on-die, Memory Wave the identical CPU could also be installed on a new motherboard, with an updated northbridge to use newer memory. Some microprocessors within the nineties, such because the DEC Alpha 21066 and HP PA-7300LC, had built-in memory controllers; however, rather than for efficiency positive factors, this was carried out to reduce the cost of systems by eliminating the need for an external memory controller.

Some CPUs are designed to have their memory controllers as devoted exterior elements that aren't part of the chipset. An instance is IBM POWER8, which uses exterior Centaur chips which can be mounted onto DIMM modules and act as memory buffers, L4 cache chips, and because the precise memory controllers. The first version of the Centaur chip used DDR3 memory however an updated version was later released which can use DDR4. A number of experimental memory controllers comprise a second degree of tackle translation, along with the first degree of tackle translation carried out by the CPU's memory administration unit to improve cache and bus efficiency. Memory controllers built-in into certain Intel Core processors present memory scrambling as a feature that turns user knowledge written to the main memory into pseudo-random patterns. Memory scrambling has the potential to forestall forensic and reverse-engineering evaluation based mostly on DRAM knowledge remanence by effectively rendering numerous types of chilly boot attacks ineffective.

In current observe, this has not been achieved; memory scrambling has only been designed to deal with DRAM-related electrical issues. The late 2010s memory scrambling standards do deal with safety points and are usually not cryptographically safe or open to public revision or analysis. ASUS and Intel have their separate memory scrambling standards. ASUS motherboards have allowed the consumer to decide on which memory scrambling normal to use (ASUS or Intel) or whether to turn the feature off fully. Double information rate (DDR) memory controllers are used to drive DDR SDRAM, where knowledge is transferred on each rising and falling edges of the system's memory clock. Multichannel memory controllers are memory controllers the place the DRAM gadgets are separated onto multiple buses to permit the memory controller(s) to entry them in parallel. This increases the theoretical quantity of bandwidth of the bus by a factor of the number of channels. While a channel for each DRAM could be the ideal resolution, adding extra channels increases complexity and value.